The present invention relates generally to the field of designing integrated circuits, and more particularly to the design of integrated circuits through a synthesis process which begins with the use of a hardware description language.
For the design of digital circuits on the scale of VLSI (very large scale integration) technology, designers often employ computer aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aide in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor""s integrated circuit, such as field programmable gate arrays (FPGA). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist which can be used to create circuits in the vendor""s technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist which is specific to a particular vendor""s technology/architecture.
One operation which is often desirable in this process is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as xe2x80x9cfloor planning.xe2x80x9d A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called xe2x80x9cblocks,xe2x80x9d and then assigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and the routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
FIG. 1 illustrates a method in the prior art for performing floorplanning and designing an integrated circuit (IC). In operation 10, a logic design, in an HDL code is submitted to an HDL compiler and is compiled. In operation 12, the compiled HDL description produces a technology independent RTL netlist which may be graphically displayed to a designer. FIG. 2A shows an example of a display 51 which includes a display of the surface area 53 of an IC and which also includes a graphical display of an RTL netlist having two modules M1 and M2 which have been labeled as modules 57 and 59. Within each of these modules there is certain logic, such as clocked registers 60 and 66 as well as logic 61, 62 and 65, and an adder 63 and a multiplexer 64.
Referring back to FIG. 1, a human designer of the IC may select in operation 14 a portion of the RTL netlist and assign/allocate this portion to a designated, specific portion of an area of the IC. Referring back to FIG. 2A, for example, a designer may select certain portions of the RTL netlist graphically shown in the display 51 and assign these portions to the region R1, labeled as 55 on the surface of the IC graphically represented as surface or region 53 in FIG. 2A. The designer may perform this selection by a number of different techniques including a graphical user interface technique which allows a dragging and dropping of logic from the graphically displayed RTL netlist to the region 55. In the example shown in FIG. 2B, the user has selected and allocated the clock registers 60 and 66 as well as logic 65 and the multiplexer 64 and the adder 63 to the region R1, thereby creating a third module 73. Module M1, now labeled as 71 in FIG. 2B, still includes logic L1 and L2 while module 72 currently contains no logic as shown in FIG. 2B. The system, in response to this selection operation 14 in FIG. 1, will change the hierarchy of the RTL objects within each of the modules so that these objects are tagged with an identifier indicating the new modules to which they are assigned and the regions to which they are assigned. Referring back to FIG. 1, in operation 16, the system will map the RTL netlist after the allocation to a target architecture to generate a technology specific netlist. Then in operation 18, place and route tools, such as conventional software tools, are used to process the technology specific netlist to generate the necessary data which will be used to program or create circuitry on an IC based on the technology specific netlist.
The method of FIG. 1 does allow a human designer greater control over the final design by allowing the designer to assign or allocate portions of the design to designated regions of the IC. After this allocation, prior art systems treat these allocations as xe2x80x9chardxe2x80x9d constraints and such prior art systems do not attempt to reallocate assigned or allocated logic back into other regions of the IC. While this approach provides flexibility and control to the designer, it may also trap the design in a low performance state than could be otherwise achievable by reallocating logic after the user has allocated or specified an allocation.
Methods and apparatuses for designing an integrated circuit are described. In one exemplary method, a hardware description language code is compiled to produce a representation of logic, and a portion of this representation of logic is allocated to a first physical portion of an area of the integrated circuit. This portion is reallocated automatically, according to machine determined parameters, such that a modified portion of the representation is allocated to the first physical portion. Examples of this reallocating include moving logic between regions on the integrated circuit, replicating logic based on the regions of the integrated circuit, decomposing RTL instances into elements based on information concerning the regions, reducing logic path crossings of a region""s boundaries, and assuring that the result of the reallocation can be accommodated by the first physical portion of the integrated circuit.
Digital processing systems which are capable of performing methods of the present invention are also described. Machine readable media are described which, when executed on a digital processing system, such as a computer system, causes the system to design an integrated circuit according to at least one of the methods described herein.